SnakeBytes
The Most Flexible Reference Design
SnakeBytes has been developed jointly by EBV Elektronik, Altera, Avago Technologies, Freescale Semiconductor and National Semiconductor.
It features Linux BSP, a PCI solution for high data throughput, a local bus solution for low-latency data transmission including a local bus IP core and several industry-standard interfaces such as CAN and RS485. A flexible solution can be developed with SnakeBytes that meets client-specific I/O requirements, while at the same time offering a high degree of computing power. The I/O system is based on FPGAs and can be easily configured. If you have any questions, or need application support and development expertise, please contact your local EBV Elektronik partner, Europe’s leading specialist in semiconductor distribution.
Key Features
- Altera SOPC builder for high-end processor applications. FPGAs are based on Stratix® II or Cyclone® III
- Freescale MPC8349E Power Architecture™
SnakeBytes Local Bus Main Features:
- DBF8349
- DBF3C120
- Linux BSP
- Local Bus IP core to connect to the FPGA.
SNAKEBYTESKIT-PCI include:
- MPC8349E-mITX-GP, the FPGA base board
- DBF2S30
- Linux BSP
- PCI IP*core
Applications Examples
Price & Inventory
Certifications
Tools
Software:
- Linux BSP
At the same time, emlix GmbH has developed an embedded Linux package specifically for the SnakeBytesKIT. This Linux package supports the configurable peripherals of the FPGA extension board with a modular driver layer and is a component of the delivered SnakeBytesKIT software package.
The Linux BSP provided with the SnakeBytesKIT is based on Freescale's Linux Target Image Builder (LTIB) for the RioGrande board. It easily supports any number of FPGA instances and I/O modules: an LCD controller with dedicated SRAM and simple 2D acceleration, a high-speed dual ADC module, a CAN module as well as others. Accompanying demo applications show how to utilise this reference design from within the Linux system.
As an additional service and to enable your access to the benefits of the embedded Linux world, emlix provides introductory training on the SnakeBytesKIT as well as project-specific support and development services.
- ALTERA Quartus II
With SnakeBytes Altera recommends the full version of the Quartus II software. Within the Quartus II design software, the SOPC Builder is also shipped.The SOPC Builder is a tool where you can select the IP, select the connection, and generate your system.
Hardware
MPC8349E-mITX-GP
The MPC8349E-mITX-GP development board demonstrates the capabilities of Freescale’s MPC8349E processor and is designed to enable fast and easy evaluation of the Power Architecture™. The board supports a Gigabit Ethernet port, a high-speed USB port, several serial I/O channels and a PCI slot. The MPC8349E-mITX-GP is delivered with a pre-installed BSP.
DBF2S30
The DBF2S30 board contains a powerful Stratix® II FPGA. This device is connected using a PCI interface to the MPC8349EmTIXGP board. Seven additional I/O Slots are available on
the board; these can be populated with such as modules to provide support for interfaces or components like LCD graphics displays, CAN, SRAM, SDRAM or Ethernet. Each of these
modules is delivered with a matching configurable SOPC Builder IP* component so that you can easily create a system in the FPGA that drives the hardware on the module. This makes adding the module driver IP to your FPGA system as easy as adding the additional hardware modules to the board.
DBF8349
The DBF8349 processor module provides a high performance(MPC8349-633 MHz) processor with a low latency, high data bandwidth local bus interface to connect to the DBF3C120’s FPGA device and DBF I/O modules.
DBF3C120
The DBF3C120 board contains the largest low cost Cyclone® III FPGA from Altera. The device contains 120 K LEs and 4 Kbit RAM. The Board supports a 32-bit PCI connector and seven I/O Slots which can be populated with modules to provide support for interfaces or components like LCD graphics displays, CAN, SRAM, SDRAM or Ethernet. Most of these modules are delivered with a matching configurable SOPC Builder IP* component so that you can easily create a system in the FPGA that drives the hardware on the module.
SNAKEBYTESKIT I/O MODULES
DBF-ADC
Dual channel ADC module based on ADC14155 with 14-bit resolution, 155 Msps sampling rate and SMA input connectors. SOPC Builder IP component supports high-speed data
acquisition into on-chip FPGA RAM. Control register to adjust the sampling frequency, start the acquisition of a given number of samples and IRQ control for sampling ready flag.
DBF-COM1
Communication module with physical drivers for 2 x CAN, 4 x RS-485 and 1 x RS-232. SOPC Builder components provided for CAN (www.ifi-pld.de) and UARTs for RS-485
and RS-232. Beside the standard UART, a 16550-compatible UART is available from www.maco-engineering.de
DBF-SDRAM1
32-bit 128 MByte SDRAM module, compliant with standard SOPC Builder SDRAM component
DBF-SRAM1
2 MByte Fast SRAM and 8 MByte Flash compliant with standard SOPC Builder SDRAM components
DBF-FLASH1-192
Flash Module with 192 Mbyte of NOR Flash, with SOPC Builder component
DBF-DVI-IN
DVI input module based on TI TFP401 with standard DVI connector.
DBF-DVI-OUT
DVI output module based on TI TFP401
DBF-PHY2
Dual industrial RJ45 Ethernet connections driven by NSC DP83849 PHY device, with SOPC-Builder 10/100 MAC IP component
DBF-PHY3
Dual Industrial fibre optic Ethernet connection driven by NSC DP83849 PHY device and Avago AFBR-5978 fibreoptic transceiver, with SOPC-Builder 10/100 MAC IP component
DBF-PHY4
Dual industrial RJ45 Ethernet connections driven by NSC DP83865 10/100/1000 Mbit Phy
DBF-TFT1/3
Interface for LVDS (3 + 1) or (4 + 1) with inverter power supply connector and touch screen controller (based on TI TSC2200). DBF-TFT1 fits on DBF2S30, DBF-TFT3 fits on DBF3C120
DBF-TST1
Prototyping module with 40 I/O Signals and 16 LEDs
Block Diagram MPC8340E-mlTX-GP
Block Diagram DBF8349
Other Information
IP Information
Altera: The PCI IP Core from Altera has now been in the market for more than 5 years. With the SnakeBytes board a PCI IP core target @ 32-bit/ 33MHz will be provided. The IP modules will be delivered in Verilog HDL and VHDL. The PCI core 32-bit/33MHz target can be evaluated free-of-charge as long as the target hardware and development software Quartus II are connected to each other, for example through USB. This feature is called OpenCore Plus.
IP Information (Local Bus)
The Local Bus IP core provides a low-latency interface between the PPC processor and the Altera FPGA. There are two independent interfaces available: The memory mapped interface and the Avalon interface. The memory mapped interface is optimised for highest data throughput and lowest latency. On the FPGA side, peripherals can be directly connected to this interface. The Avalon interface supports the SOPC Builder with the easy way to set up a peripheral system without VHDL programming. The IP-LBUS is available as an OpenCore Plus version for development.
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