There were many fragmented answers to these challenges in the past; Altera’s latest PLD families address all of these issues. Altera’s low cost Cyclone III FPGAs are based on a 65 nm low power process from TSMC. The transistors in these devices have multiple threshold voltages, variable channel lengths and variable gate thicknesses used for non-speed critical transistors. The smaller process and these transistor techniques give Cyclone III up to 50% lower power advantage over previous Cyclone devices. Stratix III devices represent a major evolutionary step in power management by using a smaller die geometry (65 nm), selectable core voltage (0.9/1.1 V), programmable power technology and Dynamic Onchip Termination. Both the static and dynamic power consumption of these devices have been reduced significantly. All of the core blocks such as ALM, memories and DSP have been completely redesigned for the 65 nm technology. All of the operational modes have also been optimised for AC (least amount of switching activity) and for DC for all unused circuitry. To utilize the power efficient resources of these PLDs, synthesis and Place & Route tools need to apply appropriate algorithms. For both Cyclone and Stratix series FPGAs, the Quartus® II design software supports power driven compilation. Altera’s innovative design solutions combine optimized process technology with robust tool support, enabling design engineers to implement highly flexible, low power electronic systems for all kind of applications.