Best-in-Class Features Stratix II devices improve on the features that set new standards in FPGAs (Figure 1). New device capabilities such as the new logic structure and design security technology round out the industry's most advanced FPGA feature set. New Logic Structure - New and innovative logic structure based on adaptive logic modules (ALMs) that packs more logic into less area and enables faster performance
Dedicated arithmetic functionality to efficiently implement adder trees and other computationally intensive functions High-Speed I/O Signaling & Interfaces - 1-Gbps source-synchronous I/O signaling performance in dedicated serialization/deserialization (SERDES) circuitry
- Dynamic phase alignment (DPA) circuitry accelerates maximum performance by dynamically resolving external board and internal device skew
- Support for differential I/O signaling levels, including HyperTransport?, LVDS, LVPECL, and differential SSTL and HSTL
External Memory Interfaces - Support for the latest external memory interfaces in dedicated circuitry, including DDR2 SDRAM, RLDRAM II, and QDRII SRAM devices
- Sufficient bandwidth and I/O pins to support interfacing with multiple, standard 64-bit or 72-bit, 168-/144-pin dual inline memory modules (DIMMs)
Design Security - Brings programmable logic functionality and benefits to new applications requiring design security
- 128-bit advanced encryption standard (AES) design security using configuration bitstream encryption technology
- Key securely stored in FPGA and does not require battery backup or consume logic resources
TriMatrix™ Memory - Up to 9 Mbits of memory in three block sizes: M-RAM, M4K, and M512 blocks
- Includes parity bits for error checking
- Performance up to 370 MHz
- Mixed-width data and mixed-clock modes
Digital Signal Processing (DSP) Blocks - More DSP block bandwidth with up to 4X more DSP bandwidth than Stratix devices
- Dedicated multiplier, pipeline, and accumulate circuitry
- New rounding and saturation support in Q1.15 format in each DSP block
- Maximized performance of up to 370 MHz
Clock Management Circuitry - Up to 12 on-chip phase-locked loops (PLLs) for device and board clock management
- Dynamic PLL reconfiguration allowing on-the-fly PLL parameter changes
- Redundant clock switchover for error recovery and multi-clock systems
On-Chip Termination -
On-chip, differential and series termination reducing board design complexity and cost Remote System Upgrades - Remote system upgrades for reliable and safe deployment of in-system upgrades and bug fixes
- Dedicated watchdog circuitry ensures proper functionality after update
Figure 1: Stratix II Device Floorplan |