Both alternatives support a large number of I/O modules offering a wide range of interface options such us: RS-232, RS-485, CAN, copper and fibre industrial Ethernet, DVI-IN, DVI-OUT and TFT LVDS interface.
Additionally, several memory extension modules are provided for both alternatives: 128MByte SDRAM Module, and 2MByte Fast SRAM plus 8MByte Flash.
Software
Linux BSP
At the same time, emlix GmbH has developed an embedded Linux package specifically for the SnakeBytesKIT. This Linux package supports the configurable peripherals of the FPGA extension board with a modular driver layer and is a component of the delivered SnakeBytesKIT software package.
The Linux BSP provided with the SnakeBytesKIT is based on Freescale's Linux Target Image Builder (LTIB) for the RioGrande board. It easily supports any number of FPGA instances and I/O modules: an LCD controller with dedicated SRAM and simple 2D acceleration, a high-speed dual ADC module, a CAN module as well as others. Accompanying demo applications show how to utilise this reference design from within the Linux system. As an additional service and to enable your access to the benefits of the embedded Linux world, emlix provides introductory training on the SnakeBytesKIT as well as project-specific support and development services. ALTERA Quartus II With SnakeBytes Altera recommends the full version of the Quartus II software. Within the Quartus II design software, the SOPC Builder is also shipped.The SOPC Builder is a tool where you can select the IP, select the connection, and generate your system.
IP Information
ALTERA
The PCI IP Core from Altera has now been in the market for more than 5 years. With the SnakeBytes board a PCI IP core target @ 32-bit/ 33MHz will be provided. The IP modules will be delivered in Verilog HDL and VHDL. The PCI core 32-bit/33MHz target can be evaluated free-of-charge as long as the target hardware and development software Quartus II are connected to each other, for example through USB. This feature is called OpenCore Plus.
IP Information (Local Bus) The Local Bus IP core provides a low-latency interface between the PPC processor and the Altera FPGA. There are two independent interfaces available: The memory mapped interface and the Avalon interface. The memory mapped interface is optimised for highest data throughput and lowest latency. On the FPGA side, peripherals can be directly connected to this interface. The Avalon interface supports the SOPC Builder with the easy way to set up a peripheral system without VHDL programming. The IP-LBUS is available as an OpenCore Plus version for development.
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